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| FULLFLEX FULLFLEX tm synchronous sdr dual port sram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-06082 rev. *k revised may 31, 2011 FULLFLEX ? synchronous sdr dual port sram features true dual port memory enables simultaneous access to the shared array from each port synchronous pipelined operation with single data rate (sdr) operation on each port ? sdr interface at 200 mhz ? up to 28.8 gb/s bandwidth (200 mhz 72-bit 2 ports) selectable pipelined or flow-through mode 1.5 v or 1.8 v core power supply commercial and industrial temperature ieee 1149.1 jtag boundary scan available in 484-ball pbga ( 72) and 256-ball fbga ( 36 and 18) packages FULLFLEX72 family ? 36-mbit: 512 k 72 (cyd36s72v18) ? 18-mbit: 256 k 72 (cyd18s72v18) ? 9-mbit: 128 k 72 (cyd09s72v18) FULLFLEX36 family ? 36-mbit: 1 m 36 (cyd36s36v18) ? 18-mbit: 512 k 36 (cyd18s36v18) ? 9-mbit: 256 k 36 (cyd09s36v18) ? 2-mbit: 64 k 36 (cyd02s36v18) FULLFLEX18 family ? 36-mbit: 2 m 18 (cyd36s18v18) ? 18-mbit: 1 m 18 (cyd18s18v18) ? 9-mbit: 512 k 18 (cyd09s18v18) built in deterministic access control to manage address collisions ? deterministic flag output upon collision detection ? collision detection on back-to-back clock cycles ? first busy address readback advanced features for improved high speed data transfer and flexibility ? variable impedance matching (vim) ? echo clocks ? selectable lvttl (3.3 v), extended hstl (1.4 v to 1.9 v), 1.8 v lvcmos, or 2.5 v lvcmos io on each port ? burst counters for sequential memory access ? mailbox with interrupt flags for message passing ? dual chip enables for easy depth expansion functional description the FULLFLEX? dual port sram families consist of 2-mbit, 9-mbit, 18-mbit, and 36-mbit synchronous, true dual port static rams that are high speed, low power 1.8 v or 1.5 v cmos. two ports are provided, enabling simultaneous access to the array. simultaneous access to a location triggers deterministic access control. for FULLFLEX72 these ports operate independently with 72-bit bus widths and each port is independently configured for two pipelined stages. each port is also configured to operate in pipelined or flow through mode. the advanced features include the following: built in deterministic acce ss control to manage address collisions during simultaneous access to the same memory location variable impedance matching (vim) to improve data transmission by matching the output driver impedance to the line impedance echo clocks to improve data transfer to reduce the static power co nsumption, chip enables power down the internal circuitry. th e number of latency cycles before a change in ce0 or ce1 enables or disables the databus matches the number of cycles of read latency selected for the device. for a valid write or read to occur, activate both chip enable inputs on a port. each port contains an optional burst counter on the input address register. after externally loading the counter with the initial address, the counter increments the address internally. additional device features include a mask register and a mirror register to control counter increments and wrap around. the counter interrupt (cntint ) flags notify the host that the counter reaches maximum count value on the next clock cycle. the host reads the burst counter internal address, mask register address, and busy address on the address lines. the host also loads the counter with the address stored in the mirror register by using the retransmit functionality. mailbox interrupt flags are used for message passing, and jtag bo undary scan and asynchronous master reset (mrst ) are also available. the logic block diagram on page 2 shows these features. the FULLFLEX72 is offered in a 484-ball plastic bga package. the FULLFLEX36 and FULLFLEX18 are available in 256-ball fine pitch bga package except the 36-mbit devices which are offered in 484-ball plastic bga package. [+] feedback
FULLFLEX document number: 38-06082 rev. *k page 2 of 52 logic block diagram the logic block diagram for FULLFLEX72, FULLFLEX36, and FULLFLEX18 family follows: [1, 2, 3] ftsel l portstd[1:0] l dq[71:0] l be [7:0] l r/ w l ftsel r portstd[1:0] r dq [71:0] r be [7:0] r ce 0 r ce1 r oe r r/ w r a [20:0] l cnt/ msk l ads l cnten l cntrst l ret l cntint l c l wrp l a [20:0] r cnt/ msk r ads r cnten r cntrst r ret r cntint r c r wrp r config block config block io control io control address & counter logic address & counter logic int l trst tms tdi tdo tck jtag mrst ready r lowspd r ready l lowspd l reset logic int r busy l busy r mailboxes collision detection logic dual port array cqen l cqen r ce 0 l ce1 l oe l cq1 r cq1 r cq0 r cq0 r cq0 l cq0 l cq1 l cq1 l zq0 r zq1 r zq0 l zq1 l notes 1. the cyd36s18v18 device has 21 address bits. the cyd36s36v18 and cyd18s18v18 devices have 20 address bits. the cyd36s72v18, cy d18s36v18, and cyd09s18v18 devices have 19 address bits. the cyd18s72v18 and cyd09s36v18 devices have 18 address bits. the cyd09s72v18 device has 17 address bits. the cyd02s36v18 has 16 address bits. 2. the FULLFLEX72 family of devices has 72 data lines. the FULLFLEX 36 family of devices has 36 data lines. the FULLFLEX18 family of devices has 18 data lines. 3. the FULLFLEX72 family of devices has eigh t byte enables. the FULLFLEX36 family of de vices has four byte enables. the FULLFLEX 18 family of devices has two byte enables. [+] feedback FULLFLEX document number: 38-06082 rev. *k page 3 of 52 contents selection guide ................................................................ 9 pin definitions .................................................................. 9 selectable io standard ............................................. 11 clocking ..................................................................... 11 selectable pipelined or flow through mode .............. 11 dll ............................................................................ 11 echo clocking ........................................................... 11 deterministic access control . ................................... 11 variable impedance matching . ...................................... 12 address counter and mask register operations ...... 13 counter load operation ............................................ 13 mask load operation ................................................ 13 counter readback operation .................................... 13 mask readback operation ........................................ 13 counter reset operation .......................................... 13 mask reset operation ............................................... 13 increment operation .................................................. 15 hold operation .......................................................... 15 retransmit ................................................................. 15 counter interrupt ....................................................... 15 counting by two ....................................................... 15 counting by four ....................................................... 15 mailbox interrupts ...................................................... 15 master reset ............................................................. 18 ieee 1149.1 serial boundary sc an (jtag) ... ........... .... 18 maximum ratings ........................................................... 19 operating range ............................................................. 19 power supply requirements ... ...................................... 19 electrical characteristics ............................................... 19 electrical characteristics ............................................... 21 electrical characteristics ............................................... 24 ac test load and waveforms ....................................... 25 switching characteristics .............................................. 26 switching waveforms .................................................... 29 ordering information ...................................................... 43 512 k 72 (36-mbit) 1.8 v/1.5 v synchronous cyd36s72v18 dual port sram ...................................... 43 256 k 72 (18-mbit) 1.8 v/1.5 v synchronous cyd18s72v18 dual port sram ...................................... 43 128 k 72 (9-mbit) 1.8 v/1.5 v synchronous cyd09s72v18 dual port sram ...................................... 43 1024 k 36 (36-mbit) 1.8 v/1.5 v synchronous cyd36s36v18 dual port sram ...................................... 43 512 k 36 (18-mbit) 1.8 v/1.5 v synchronous cyd18s36v18 dual port sram ...................................... 43 256 k 36 (9-mbit) 1.8 v/1.5 v synchronous cyd09s36v18 dual port sram ...................................... 44 64 k 36 (2-mbit) 1.8 v or 1.5 v synchronous cyd02s36v18 dual port sram ...................................... 44 2048 k 18 (36-mbit) 1.8 v/1.5 v synchronous cyd36s18v18 dual port sram ...................................... 45 1024 k 18 (18-mbit) 1.8 v/1.5 v synchronous cyd18s18v18 dual port sram ...................................... 45 512 k 18 (9-mbit) 1.8 v/1.5 v synchronous cyd09s18v18 dual port sram ...................................... 45 ordering code definitions ..... .................................... 45 package diagrams .......................................................... 46 acronyms ........................................................................ 48 document conventions ................................................. 48 units of measure ....................................................... 48 document history page ................................................. 49 sales, solutions, and legal information ...................... 52 worldwide sales and design s upport ......... .............. 52 products .................................................................... 52 psoc solutions ......................................................... 52 [+] feedback document number: 38-06082 rev. *k page 4 of 52 FULLFLEX figure 1. FULLFLEX72 sdr 484-ball bga pinout (top view) 12 3 4 5 6 7 8 9 101112 13 14 1516171819 20 2122 a dnu dq61l dq59l dq57l dq54l dq51l dq48l dq45l dq42l dq39l dq36l dq36r dq39r dq42r dq45r dq48r dq51r dq54r dq57r dq59r dq61r dnu b dq63l dq62l dq60l dq58l dq55l dq52l dq49l dq46l dq43l dq40l dq 37l dq37r dq40r dq43r dq46r dq49r dq52r dq55r dq58r dq60r dq62r dq63r c dq65l dq64l vss vss dq56l dq53l dq50l dq47l dq44l dq41l dq38l dq38r dq41r dq44r dq47r dq50r dq53r dq56r vss vss dq64r dq65r d dq67l dq66l vss vss vss cq1l cq1l vss lowspdl portstd0l zq0l [4] busyl cntintl portstd1l dnu cq1r cq1r vss vss vss dq66r dq67r e dq69l dq68l vddiol vss vss vddiol vddiol vd diol vddiol vddiol vttl vttl vttl vddior v ddior vddior vddior dn u vss vddior dq68r dq69r f dq71l dq70l ce1l ce0l vddiol vddi ol vddiol vddiol vddiol vcore vcore vcore vcore vddior vddior vddior vddior vddior ce0r ce1r dq70r dq71r g a0l a1l retl be4l vddiol vddiol vrefl vss vss vss vss vss vss vss vss vrefr vddior vddior be4r retr a1r a0r h a2l a3l wrpl be5l vddiol vddiol vss vss vss vss vss vss vss vss vss vss vddior vddior be5r wrpr a3r a2r j a4l a5l readyl be6l vddiol vddiol vss vss vss vss vss vss vss vss vss vss vddior vddior be6r readyr a5r a4r k a6l a7l zq1l [4, 5] be7l vttl vcore vss vss vss vss vss vss vss vss vss vss vcore vddior be7r zq1r [4, 5] a7r a6r l a8l a9l cl oel vttl vcore vss vss vss vss vss vss vss vss vss vss vcore vttl oer cr a9r a8r m a10l a11l vss be3l vttl vcore vss vss vss vss vss vss vss vss vss vss vcore vttl be3r vss a11r a10r n a12l a13l adsl be2l vddiol vcore vss vss vss vss vss vss vss vss vss vss vcore vttl be2r adsr a13r a12r p a14l a15l cnt/mskl be1l vddiol vddiol vss vss vss vss vss vss vss vss vss vss vddior vddior be1r cnt/mskr a15r a14r r a16l [8] a17l [7] cntenl be0l vddiol vddiol vss vss vss vss vss vss vss vss vss vss vddior vddior be0r cntenr a17r [7] a16r [8] t a18l [6] dnu cntrstl intl vddiol vddiol vrefl vss vss vss vss vss vss vss vss vrefr vddior vddior intr cntrstr dnu a18r [6] u dq35l dq34l r/wl cqenl vddiol vddiol vddiol vddiol vddiol vcore vcore vcore vcore vddior vddior vddi or vddior vddior cqenr r/wr dq34r dq35r v dq33l dq32l ftsell vddiol dnu vddiol vddiol vddiol vddiol vttl vttl v ttl vddior vddior vddior vddior vddior trst vddior ftselr dq32r dq33r w dq31l dq30l vss mrst vss cq0l cq0l dnu portstd1r cntintr busyr zq0r [4] portstd0r lowspdr vss cq0r cq0r vss tdi tdo dq30r dq31r y dq29l dq28l vss vss dq20l dq17l dq14l dq11l dq8l dq5l dq 2l dq2r dq5r dq8r dq11r dq14r dq17r dq20r tms tck dq28r dq29r aa dq27l dq26l dq24l dq22l dq19l dq16l dq13l dq10l dq7l dq4l dq 1l dq1r dq4r dq7r dq10r dq13r dq16r dq19r dq22r dq24r dq26r dq27r ab dnu dq25l dq23l dq21l dq18l dq15l dq12l dq9l dq6l dq3l dq0l dq0r dq3r dq6r dq9r dq12r dq15r dq18r dq21r dq23r dq25r dnu notes 4. leave this ball unconnected to disable vim. 5. this ball is applicable only for 36-mbit and dnu for 18-mbit and lower densities. 6. leave this ball unconnected for cyd18s72v18 and cyd09s72v18. 7. leave this ball unconnected for cyd09s72v18. 8. leave this ball unconnected for cyd04s72v18. [+] feedback document number: 38-06082 rev. *k page 5 of 52 FULLFLEX figure 2. FULLFLEX36 sdr 484-ball bga pinout (top view) [9] 123 45678 9 10111213141516171819202122 a dnu dnu dnu dnu dnu dq33l dq30l dq27l dq24l dq21l dq18l dq 18r dq21r dq24r dq27r dq30r dq33r dnu dnu dnu dnu dnu b dnu dnu dnu dnu dnu dq34l dq31l dq28l dq25l dq22l dq19l dq 19r dq22r dq25r dq28r dq31r dq34r dnu dnu dnu dnu dnu c dnu dnu vss vss dnu dq35l dq32l dq29l dq26l dq23l dq20l dq 20r dq23r dq26r dq29r dq32r dq35r dnu vss vss dnu dnu d dnu dnu vss vss vss cq1l cq1l vss lowspdl portstd0l zq0l [10] busyl cntintl portstd1l dnu cq1r cq1r vss vss vss dnu dnu e dnu dnu vddiol vss vss vddiol vddior vddior vddior vddior vttl vttl vttl vddiol vddiol vddiol vddiol dnu vss vddior dnu dnu f dnu dnu ce1l ce0l vddiol vddiol vddior vddior vddior vcore vcore vcore vco re vddiol vddiol vddiol vddi or vddior ce0r ce1r dnu dnu g a0l a1l retl be2l vddiol vddiol vrefl vss vss vss vss vss vss vss vss vrefr vddior vddior be2r retr a1r a0r h a2l a3l wrpl be3l vddiol vddiol vss vss vss vss vss vss vss vss vss vss vddior vddior be3r wrpr a3r a2r j a4l a5l readyl dnu vddiol vddiol vss vss vss vss vss vss vss vss vss vss vddior vddior dnu readyr a5r a4r k a6l a7l zq1l [10] dnu vttl vcore vss vss vss vss vss vss vss vss vss vss vcore vddior dnu zq1r [10] a7r a6r l a8l a9l cl oel vttl vcore vss vss vss vss vss vss vss vss vss vss vcore vttl oer cr a9r a8r m a10l a11l vss dnu vttl vcore vss vss vss vss vss vss vss vss vss vss vcore vttl dnu vss a11r a10r n a12l a13l adsl dnu vddiol vcore vss vss vss vss vss vss vss vss vss vss vcore vttl dnu adsr a13r a12r p a14l a15l cnt/mskl be1l vddiol vddiol vss vss vss vss vss vss vss vss vss vss vddior vddior be1r cnt/mskr a15r a14r r a16l a17l cntenl be0l vddiol vddiol vss vss vss vss vss vss vss vss vss vss vddior vddior be0r cntenr a17r a16r t a18l a19l cntrstl intl vddiol vddiol vrefl vss vss vss vss vss vss vss vss vrefr vddior vddior intr cntrstr a19r a18r u dnu dnu r/wl cqenl vddiol vddiol vddior vddior vddi or vcore vcore vcore vcore vddiol vddi ol vddiol vddior vddior cqenr r/wr dnu dnu v dnu dnu ftsell vddiol dnu vddior vddior vddior vddior vttl vttl vttl vddiol vddiol vddiol vddiol v ddior trst vddior ftselr dnu dnu w dnu dnu vss mrst vss cq0l cq0l dnu portstd1r cntintr busyr zq0r [10] portstd0r lowspdr vss cq0r cq0r vss tdi tdo dnu dnu y dnu dnu vss vss dnu dq17l dq14l dq11l dq8l dq5l dq2l d q2r dq5r dq8r dq11r dq14r dq17r dnu tms tck dnu dnu aa dnu dnu dnu dnu dnu dq16l dq13l dq10l dq7l dq4l dq1l dq1r dq4r dq7r dq10r dq13r dq16r dnu dnu dnu dnu dnu ab dnu dnu dnu dnu dnu dq15l dq12l dq9l dq6l dq3l dq0l dq0r dq3r dq6r dq9r dq12r dq15r dnu dnu dnu dnu dnu notes 9. use this pinout only for device cy d36s36v18 of the FULLFLEX36 family. 10. leave this ball unconnected to disable vim. [+] feedback document number: 38-06082 rev. *k page 6 of 52 FULLFLEX figure 3. FULLFLEX18 sdr 484-ball bga pinout (top view) [11] 123 45678 9 10111213141516171819202122 a dnu dnu dnu dnu dnu dnu dnu dnu dq15l dq12l dq9l dq9r dq12r dq15r dnu dnu dnu dnu dnu dnu dnu dnu b dnu dnu dnu dnu dnu dnu dnu dnu dq16l dq13l dq10l dq10r dq13r dq16r dnu dnu dnu dnu dnu dnu dnu dnu c dnu dnu vss vss dnu dnu dnu dnu dq17l dq14l dq11l dq11r dq14r dq17r dnu dnu dnu dnu vss vss dnu dnu d dnu dnu vss vss vss cq1l cq1l vss lowspdl portstd0l zq0l [12] busyl cntintl portstd1l dnu cq1r cq1r vss vss vss dnu dnu e dnu dnu vddiol vss vss vddiol vddior vddior vddior vddior vt tl vttl vttl vddiol vddiol vddiol vddiol dnu vss vddior dnu dnu f dnu dnu ce1l ce0l vddiol vddiol vddior vddior vddior vcore vcore vcore vcore vddiol v ddiol vddiol vddior vddior ce0r ce1r dnu dnu g a0l a1l retl be1l vddiol vddiol vrefl vss vss vss vss vss vss vss vss vrefr vddior vddior be1r retr a1r a0r h a2l a3l wrpl dnu vddiol vddiol vss vss vss vss vss vss vss vss vss vss vddior vddior dnu wrpr a3r a2r j a4l a5l readyl dnu vddiol vddiol vss vss vss vss vss vss vss vss vss vss vddior vddior dnu readyr a5r a4r k a6l a7l zq1l [12] dnu vttl vcore vss vss vss vss vss vss vss vss vss vss vcore vddior dnu zq1r [12] a7r a6r l a8l a9l cl oel vttl vcore vss vss vss vss vss vss vss vss vss vss vcore vttl oer cr a9r a8r m a10l a11l vss dnu vttl vcore vss vss vss vss vss vss vss vss vss vss vcore vttl dnu vss a11r a10r n a12l a13l adsl dnu vddiol vcore vss vss vss vss vss vss vss vss vss vss vcore vttl dnu adsr a13r a12r p a14l a15l cnt/mskl dnu vddiol vddiol vss vss vss vss vss vss vss vss vss vss vddior vddior dnu cnt/mskr a15r a14r r a16l a17l cntenl be0l vddiol vddiol vss vss vss vss vss vss vss vss vss vss vddior vddior be0r cntenr a17r a16r t a18l a19l cntrstl intl vddiol vddiol vrefl vss vss vss vss vss vss vss vss vrefr vddior vddior intr cntrstr a19r a18r u a20l dnu r/wl cqenl vddiol vddiol vddior vddior vddi or vcore vcore vcore vcore vddiol vddi ol vddiol vddior vddior cqenr r/wr dnu a20r v dnu dnu ftsell vddiol dnu vddior vddior vddior vddior vttl vttl vttl vddiol vddiol vddiol vddiol v ddior trst vddior ftselr dnu dnu w dnu dnu vss mrst vss cq0l cq0l dnu portstd1r cntintr busyr zq0r [12] portstd0r lowspdr vss cq0r cq0r vss tdi tdo dnu dnu y dnu dnu vss vss dnu dnu dnu dnu dq8l dq5l dq2l dq2r dq5r dq8r dnu dnu dnu dnu tms tck dnu dnu aa dnu dnu dnu dnu dnu dnu dnu dnu dq7l dq4l dq1l dq1r dq4r dq7r dnu dnu dnu dnu dnu dnu dnu dnu ab dnu dnu dnu dnu dnu dnu dnu dnu dq6l dq3l dq0l dq0r dq3r dq6r dnu dnu dnu dnu dnu dnu dnu dnu notes 11. use this pinout only for device cyd36s18v18 of the FULLFLEX18 family. 12. leave this ball unconnected to disable vim. [+] feedback document number: 38-06082 rev. *k page 7 of 52 FULLFLEX figure 4. FULLFLEX36 sdr 256-ball bga (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a dq32l dq30l dq28l dq26l dq24l dq22l dq20l dq18l dq18r dq20r dq22r dq24r dq26r dq28r dq30r dq32r b dq33l dq31l dq29l dq27l dq25l dq23l dq21l dq19l dq19r dq21r dq23r dq25r dq27r dq29r dq31r dq33r c dq34l dq35l retl intl cq1l cq1l dnu trst mrst zq0r [13] cq1r cq1r intr retr dq35r dq34r d a0l a1l wrpl vrefl ftsell lowspdl vss vttl vttl vss lowspdr ftselr vrefr wrpr a1r a0r e a2l a3l ce0l ce1l vddiol vddiol vddiol vcore vco re vddior vddior vddior ce1r ce0r a3r a2r f a4l a5l cntintl be3l vddiol vss vss vss vss vss vss vddior be3r cntintr a5r a4r g a6l a7l busyl be2l zq0l [13] vss vss vss vss vss vss vddior be2r busyr a7r a6r h a8l a9l cl vttl vcore vss vss vss vss vss vss vcore vttl cr a9r a8r j a10l a11l vss portstd1l vcore vss vss vss vss vss vss vcore portstd1r vss a11r a10r k a12l a13l oel be1l vddiol vss vss vss vss vss vss vddior be1r oer a13r a12r l a14l a15l adsl be0l vddiol vss vss vss vss vss vss vddior be0r adsr a15r a14r m a16l [16] a17l [15] r/wl cqenl vddiol vddiol vddiol vcore vco re vddior vddior vddior cqenr r/wr a17r [15] a16r [16] n a18l [14] dnu cnt/mskl vrefl portstd0l readyl dnu vttl vttl dnu readyr portstd0r vrefr cnt/mskr dnu a18r [14] p dq16l dq17l cntenl cntrstl cq0l cq0l tck tms tdo tdi cq0r cq0r cntrstr cntenr dq17r dq16r r dq15l dq13l dq11l dq9l dq7l dq5l dq3l dq1l dq1r dq3r dq5r dq7r dq9r dq11r dq13r dq15r t dq14l dq12l dq10l dq8l dq6l dq4l dq2l dq0l dq0r dq2r dq4r dq6r dq8r dq10r dq12r dq14r notes 13. leave this ball unconnected to disable vim. 14. leave this ball unconnected for cyd09s36v18 and cyd02s36v18. 15. leave this ball unconnected for cyd02s36v18. 16. leave this ball unconnected for cyd02s36v18. [+] feedback document number: 38-06082 rev. *k page 8 of 52 FULLFLEX figure 5. FULLFLEX18 sdr 256-ball bga (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a dnu dnu dnu dq17l dq16l dq13l dq12l dq9l dq9r dq12r dq13r dq16r dq17r dnu dnu dnu b dnu dnu dnu dnu dq15l dq14l dq11l dq10l dq10r dq11r dq14r dq15r dnu dnu dnu dnu c dnu dnu retl intl cq1l cq1l dnu trst mrst zq0r [17] cq1r cq1r intr retr dnu dnu d a0l a1l wrpl vrefl ftsell lowspdl vss vttl vttl vss lowspdr ftselr vrefr wrpr a1r a0r e a2l a3l ce0l ce1l vddiol vddiol vddiol vcore vco re vddior vddior vddior ce1r ce0r a3r a2r f a4l a5l cntintl dnu vddiol vss vss vss vss vss vss vddior dnu cntintr a5r a4r g a6l a7l busyl dnu zq0l [17] vss vss vss vss vss vss vddior dnu busyr a7r a6r h a8l a9l cl vttl vcore vss vss vss vss vss vss vcore vttl cr a9r a8r j a10l a11l vss portstd1l vcore vss vss vss vss vss vss vcore portstd1r vss a11r a10r k a12l a13l oel be1l vddiol vss vss vss vss vss vss vddior be1r oer a13r a12r l a14l a15l adsl be0l vddiol vss vss vss vss vss vss vddior be0r adsr a15r a14r m a16l a17l r/wl cqenl vddiol vddiol vddi ol vcore vcore vddior v ddior vddior cqenr r/wr a17r a16r n a18l [19] a19l [18] cnt/mskl vrefl portstd0l readyl dnu vttl vttl dnu readyr portstd0r vrefr cnt/mskr a19r [18] a18r [19] p dnu dnu cntenl cntrstl cq0l cq0l tck tms tdo tdi cq0r cq0r cntrstr cntenr dnu dnu r dnu dnu dnu dnu dq6l dq5l dq2l dq1l dq 1r dq2r dq5r dq6r dnu dnu dnu dnu t dnu dnu dnu dq8l dq7l dq4l dq3l dq0l dq 0r dq3r dq4r dq7r dq8r dnu dnu dnu notes 17. leave this ball unconnected to disable vim. 18. leave this ball unconnected for cyd09s18v18. 19. leave this ball unconnected for cyd04s18v18. [+] feedback FULLFLEX document number: 38-06082 rev. *k page 9 of 52 selection guide parameter -200 -167 unit f max [21] 200 167 mhz maximum access time (clock to data) 3.3 4.0 ns typical operating current i cc 800 [20] 700 [20] ma typical standby current for i sb3 (both ports cmos level) 210 [20] 210 [20] ma pin definitions left port right port description a[20:0] l a[20:0] r address inputs . [22] dq[71:0] l dq[71:0] r data bus input and output . [23] be [7:0] l be [7:0] r byte select inputs . [24] asserting these signals enables read and write operations to the corresponding bytes of the memory array. busy l busy r port busy output . when there is an address match and both chip enables are active for both ports, an external busy signal is asserted on the fifth clock cycles from when the collision occurs. c l c r clock signal . maximum clock input rate is f max . ce0 l ce0 r active low chip enable input . ce1 l ce1 r active high chip enable input . cqen l cqen r echo clock enable input . assert high to enable echo clocking on respective port. cq0 l cq0 r echo clock signal output for dq[35:0] for FULLFLEX72 devices . echo clock signal output for dq[17:0] for FULLFLEX36 devices. echo clock signal output for dq[8:0] for FULLFLEX18 devices. cq0 l cq0 r inverted echo clock signal output for dq[35:0] for FULLFLEX72 devices . inverted echo clock signal output for dq[17:0] for FULLFLEX36 devices. inverted echo clock signal output for dq[8:0] for FULLFLEX18 devices. cq1 l cq1 r echo clock signal output for dq[71:36] for FULLFLEX72 devices . echo clock signal output for dq[35:18] for FULLFLEX36 devices. echo clock signal output for dq [17:9] for FULLFLEX18 devices. cq1 l cq1 r inverted echo clock signal output for dq[71:36] fo r FULLFLEX72 devices . inverted echo clock signal output for dq[35:18] for FULLFLEX36 devices. inverted echo clock signal output for dq[17:9] for FULLFLEX18 devices. zq[1:0] l zq[1:0] r vim output impedance matching input . [25] to use, connect a calibrating resistor between zq and ground. the resistor must be five times la rger than the intended line impedance driven by the dual port. assert high or leave dnu to disable vim. oe l oe r output enable input . this asynchronous signal must be asserted low to enable the dq data pins during read operations. int l int r mailbox interrupt flag output . the mailbox permits communications between ports. the upper two memory locations are us ed for message passing. int l is asserted low when the right port writes to the mailbox location of the left port, an d vice versa. an interrupt to a port is deasserted high when it reads the contents of its mailbox. lowspd l lowspd r port low speed select input . assert this pin low to disable the dll. in flow through mode, this pin needs to be asserted low. notes 20. for 18 mbit x72 commercial configuration only, refer to electrical characteristics on page 19 for complete information. 21. sdr mode with two pipelined stages. 22. the cyd36s18v18 device has 21 address bits. the cyd36s36v18 and cyd18s18v18 devices have 20 address bits. the cyd36s72v18, c yd18s36v18, and cyd09s18v18 devices have 19 address bits. the cyd18s72v18 and cyd09s36v18 devices have 18 addre ss bits. the cyd09s72v18 device has 17 address bits. the cyd02s36v18 has 16 address bits. 23. the FULLFLEX72 family of devices has 72 data lines. the FULLFLEX36 family of devi ces has 36 data lines. the FULLFLEX18 famil y of devices has 18 data lines. 24. the FULLFLEX72 family of devices has eight byte enables. the fu llflex36 family of devices has four byte enables. the fullfle x18 family of devices has two byte enables. 25. the pin zq[1] is applicable only for 36 mbit devices. this pin is dnu for 18 mbit and lower density devices. [+] feedback FULLFLEX document number: 38-06082 rev. *k page 10 of 52 portstd[1:0] l [26] portstd[1:0] r [26] port clock/address/control/data/echo clock/i/o standard select input . assert these pins low/low for lvttl, low/high for hstl, high/low for 2.5 v lvcmos, and high/high for 1.8 v lvcmos, respectively. these pins are driven by vttl referenced levels. r/w l r/w r read/write enable input . assert this pin low to write to, or high to read from the dual port memory array. ready l ready r port dll ready output . this signal is asserted low when the dll and variable impedance matching circuits complete calibration. this is a wired or capable output. cnt/msk l cnt/msk r port counter/mask select input . counter control input. ads l ads r port counter address load strobe input . counter control input. cnten l cnten r port counter enable input . counter control input. cntrst l cntrst r port counter reset input . counter control input. cntint l cntint r port counter in terrupt output . this pin is assert ed low one cycle before the unmasked portion of the counter is incremented to all ?1s?. wrp l wrp r port counter wrap input . when the burst counter reaches the maximum count, on the next counter increment wrp is set low to load the unmasked counter bits to 0. it is set high to load the counter with the value stored in the mirror register. ret l ret r port counter retransmit input . assert this pin low to reload the initial address for repeated access to the same segment of memory. vref l vref r port external hstl io reference input . this pin is left dnu when hstl is not used. vddio l vddio r port data io power supply . ftsel l ftsel r port flow through mode select input . assert this pin low to select flow through mode. assert this pin high to se lect pipelined mode. mrst master reset input . mrst is an asynchronous input signal and affects both ports. asserting mrst low performs all of the reset functions as described in the text. a mrst operation is required at power up. this pin is driven by a vddio l referenced signal. tms jtag test mode select input . it controls the advance of jtag tap state machine. state machine transitions occur on the rising edge of tck. operation for lvttl or 2.5 v lvcmos. tdi jtag test data input . data on the tdi input is shifted serial ly into selected r egisters. operation for lvttl or 2.5 v lvcmos. trst jtag reset input . operation for lvttl or 2.5 v lvcmos. tck jtag test clock input . operation for lvttl or 2.5 v lvcmos. tdo jtag test data output . tdo transitions occur on the falling edge of tck. tdo is normally tri-stated except when captured data is shifted ou t of the jtag tap. operation for lvttl or 2.5 v lvcmos. vss ground inputs . vcore device core power supply . vttl lvttl power supply . pin definitions (continued) left port right port description note 26. portstd[1:0] l and portstd[1:0] r have internal pull-down resistors. [+] feedback FULLFLEX document number: 38-06082 rev. *k page 11 of 52 selectable io standard the FULLFLEX device families offer the option to choose one of the four port standards for the device. each port independently selects standards from single ended hstl class i, single ended lvttl, 2.5 v lvcmos, or 1.8 v lvcmos. the selection of the standard is determined by the portstd pins for each port. these pins must be connected to an lvttl power suppy. this determines the input clock, address, control, data, and echo clock standard for each port as shown in table 1 . clocking separate clocks synch ronize the operations on each port. each port has one clock input c. in this mode, all the transactions on the address, control, and data are on the c rising edge. all transactions on the address, c ontrol, data input, output, and byte enables occur on the c rising edge. selectable pipelined or flow through mode to meet data rate and throughput requirements, the FULLFLEX families offer selectable pipelined or flow through mode. echo clocks are not supported in flow through mode and the dll must be disabled. flow through mode is selected by the ftsel pin. strapping this pin high selects pipelined mode. strapping this pin low selects flow through mode. dll the FULLFLEX familes of devices have an on-chip dll. enabling the dll reduces the clock to data valid (t cd ) time enabling more setup time for the receiving devi ce. in flow through mode, the dll must be disabled. this is selectable by strapping lowspd low. whenever the operating frequency is altered beyond the clock input cycle to cycle jitter specif ication, reset the dll, followed by 1024 clocks before any valid operation. lowspd pins are used to reset the dlls for a single port independent of all other circuitry. mrst is used to reset all dlls on the chip. for more information on dll lock and reset time, see master reset on page 18 . echo clocking as the speed of data increases, on-board delays caused by parasitics make it extremely diff icult to provide accurate clock trees. to counter this problem, the FULLFLEX families incorporate echo clocks. echo clocks are enabled on a per port basis. the dual port receives input clocks that are used to clock in the address and control signals for a read operation. the dual port retransmits the input clocks re lative to the data output. the buffered clocks are provided on the cq1/cq1 and cq0/cq0 outputs. each port has a pair of echo clocks. each clock is associated with half the data bits . the output clock matches the corresponding ports io configuration. to enable echo clock outputs, ti e cqen high. to disable echo clock outputs, tie cqen low. deterministic access control deterministic access control is provided for ease of design. the circuitry detects when both ports access the same location and provides an external busy flag to the port on which data is corrupted. the collision detection logic saves the address in conflict (busy address) to a readable register. in the case of multiple collisions, the first busy address is written to the busy address register. if both ports access the same location at the same time and only one port is doing a write, if t ccs is met, then the data written to and read from the address is valid data. for example, if the right port is reading and the left port is writing and the left ports clock meets t ccs , then the data read from th e address by the right port is the old data. in the same case , if the right ports clock meets t ccs , then the data read out of the a ddress from the right port is the new data. in the above case, if t ccs is violated by the either ports clock with respect to the other port and the right port gets the external busy flag, the data from the right port is corrupted. table 3 on page 12 shows the t ccs timing that must be met to guarantee the data. table 4 on page 12 shows that, in the case of the left port writing and the right port reading, when an external busy flag is asserted on the right port, the data read out of the device is not guaranteed. the value in the busy address register is read back to the address lines. the required input co ntrol signals for this function are shown in table 7 on page 14 . the value in the busy address register is read out to the address lines t ca after the same amount of latency as a data read operation. after an initial address match, the busy flag is asserted and the address under contention is saved in the busy address register. all the following table 1. port standard selection portstd1 portstd0 i/o standard vss vss lvttl vss vttl hstl vttl vss 2.5 v lvcmos vttl vttl 1.8 v lvcmos table 2. data pin assignment be pin name data pin name be [7] dq[71:63] be [6] dq[62:54] be [5] dq[53:45] be [4] dq[44:36] be [3] dq[35:27] be [2] dq[26:18] be [1] dq[17:9] be [0] dq[8:0] figure 6. sdr echo clock delay input clock echo clock data out echo clock [+] feedback FULLFLEX document number: 38-06082 rev. *k page 12 of 52 address matches enable to generate the busy flag. however, none of the addresses are saved into the busy address register. when a busy readback is performed, the address of the first match that happens at least two clocks cycles after the busy readback is saved into the busy address register. variable impedance matching each port contains a variable impedance matching circuit to set the impedance of the io driver to match the impedance of the on-board traces. the impedance is set for all outputs except jtag and is done by port. to take advantage of the vim feature, connect a calibrating resistor (rq) that is five times the value of the intended line impedance from the zq [1:0] [27] pin to v ss . the output impedance is then adjusted to account for drifts in supply voltage and temperature every 102 4 clock cycles. if a port?s clock is suspended, the vim circuit retain s its last setting until the clock is restarted. on restart, it then resumes periodic adjustment. in the case of a significant change in device temperature or supply voltage, recalibration happens every 1024 clock cycles. a master reset initializes the vim circuitry. ta b l e 5 shows the vim parameters and table 6 describes the vim operation modes. to disable vim, connect the zq pin to vddio of the relative supply for the ios before a master reset. table 3. t ccs timing for all operating modes port a?early arriving port port b?late arriving port t ccs c rise to opposite c rise setup time for non corrupt data unit mode active edge mode active edge sdrcsdr ct cyc(min) ? 0.5 ns table 4. deterministic access control logic left port right port left clock right clock busy l busy r description read read x x h h no collision write read > t ccs 0 h h read old data 0> t ccs h h read new data < t ccs 0 h h read old data h l data not guaranteed 0< t ccs h h read new data h l data not guaranteed read write > t ccs 0 h h read new data 0> t ccs hhread old data < t ccs 0 h h read new data l h data not guaranteed 0< t ccs hhread old data l h data not guaranteed write write 0 > ?t ccs & < t ccs l l array data corrupted 0> t ccs l h array stores right port data > t ccs 0 h l array stores left port data table 5. variable impedance matching parameters parameter min max unit tolerance rq value 100 275 ? 2% output impedance 20 55 ? 15% reset time ? 1024 cycles ? update time ? 1024 cycles ? table 6. variable impedance matching operation rq connection output configuration 100 ? ?275 ? to v ss output driver impedance = rq/5 15% at vout = vddio/2 zq ? to vddio vim disabled. rout < 20 ?? at vout = vddio/2 note 27. the pin zq[1] is applicable only for 36 mbit devices. this pin is dnu for 18 mbit and lower density devices. [+] feedback FULLFLEX document number: 38-06082 rev. *k page 13 of 52 address counter and mask register operations [28] each port of the FULLFLEX family contains a programmable burst address counter. the burst counter contains four registers: a counter register, a mask register, a mirror register, and a busy address register. the counter register contains the address used to access the ram array. it is changed only by the master reset (mrst ), counter reset, counter load, retransmit, and counter increment operations. the mask register value affects the counter increment and counter reset operations by preventing the corresponding bits of the counter register from changi ng. it also affects the counter interrupt output (cntint ). the mask register is only changed by mask reset, mask load, and mrst . the mask load operation loads the value of the address bus into the mask register. the mask register defines the counting range of the counter register. the mask register is divided into two or three consecutive regions. zero or more 0s define the masked region and one or more 1s define the unmasked portion of the counter register. the counter register may be divided up to three regions. the region containing the least significant bits must be no more than two 0s. bits one and zero may be 10 respectively, masking the least significant counter bit and causing the counter to increment by two instead of one. if bits one and zero are 00, the two least significant bits are masked and the counter increments by four instead of one. for example, in the case of a 256 k 72 configuration, a mask register value of 003fc divides the mask register into three regions. with bit 0 being the least significant bit and bit 17 being the most significant bit, the two least significant bits are masked, the next eight bits are unmasked, and the remaining bits are masked. the mirror register reloads a counter register on retransmit operations (see retransmit on page 15 ) and wrap functions (see counter interrupt on page 15 below). the last value loaded into the counter register is stored in the mirror register. the mirror register is only changed by master reset (mrst ), counter reset, and counter load. table 7 on page 14 summarizes the operations of these registers and the required input control si gnals. all signals except mrst are synchronized to the ports clock. counter load operation [28] for both non-burst and burst read or write accesses, the external address is loaded through counter load operation as shown in table 7 on page 14 . the address counter and mirror registers are loaded with the address value presented on the address lines. this value ranges from 0 to 1fffff. mask load operation [28] the mask register is loaded with the address value presented on the address bus. this value ranges from 0 to 1fffff though not all values permit correct increment operations. permitted values are in the form of 2 n ?1, 2 n ?2, or 2 n ?4. the counter register is only segmented up to three regions. fr om the most significant bit to the least significant bit, permitted values have zero or more 0s, one or more 1s, and the least significant two bits are 11, 10, or 00. thus 1ffffe, 07ffff, and 003ffc are permitted values but 02ffff, 003ffa, and 07ffe4 are not. counter readback operation the internal value of the counte r register is read out on the address lines. the address is valid t ca after the selected number of latency cycles configured by ftsel . the data bus (dq) is tri-stated on the cycle that the address is presented on the address lines. figure 7 on page 16 shows a block diagram of this logic. mask readback operation the internal value of the mask register is read out on the address lines. the address is valid t ca after the selected number of latency cycles configured by ftsel . the data bus (dq) is tri-stated on the cycle that the address is presented on the address lines. figure 7 on page 16 shows a block diagram of the operation. counter reset operation all unmasked bits of the counter and mirror registers are reset to ?0?. all masked bits remain unchanged. a mask reset followed by a counter reset resets the counter and mirror registers to 00000. mask reset operation the mask register is reset to all 1s, that unmasks every bit of the burst counter. note 28. the cyd36s18v18 device has 21 address bits. the cyd36s36v18 and cyd18s18v18 devices have 20 address bits. the cyd36s72v18, c yd18s36v18, and cyd09s18v18 devices have 19 address bits. the cyd18s72v18 and cyd09s36v18 devices have 18 address bits. the cyd09s72v18 device has 17 address bits. the cyd02s36v18 has 16 address bits. [+] feedback FULLFLEX document number: 38-06082 rev. *k page 14 of 52 table 7. burst counter and mask register control operations the burst counter and mask register c ontrol operation for any port follows. [29, 30] c mrst cntrst cnt/msk cnten ads ret operation description x l x x x x x master reset reset address counter to all 0s, mask register to all 1s, and busy address to all 0s. h l h x x x counter reset reset counter and mirror unmasked portion to all 0s. h l l x x x mask reset reset mask register to all 1s. h h h l l x counter load for burst/external address load for non-burst load burst counter and mirror with external address value presented on address lines. h h l l l x mask load load mask register with value presented on the address lines. h h h l h l retransmit load counter with value in the mirror register. h h h l h h counter increment internally increment address counter value. h h h h h h counter hold constantly hold the address value for multiple clock cycles. h h h h l h counter readback read out counter internal value on address lines. h h l h l h mask readback read out mask register value on address lines. h h l h h l busy address readback read out first busy address after last busy address readback. hh l lhxreserved hh lhllreserved hh lhhhreserved hh hhllreserved hh hhhlreserved notes 29. ?x? = don?t care, ?h? = high, ?l? = low. 30. counter operation and mask register operation is independent of chip enables. [+] feedback FULLFLEX document number: 38-06082 rev. *k page 15 of 52 increment operation [31] after the address counter is init ially loaded with an external address, the counter can inter nally increment the address value and address the entire memory array. only the unmasked bits of the counter register are incr emented. for a counter bit to change, the corresponding bit in the mask register must be 1. if the two least significant bits of t he mask register are 11, the burst counter increments by one. if the two least significant bits are 10, the burst counter increments by tw o, and if they are 00, the burst counter increments by four. if all unmasked counter bits are incremented to 1 and wrp is deasserted, the next increment l wraps the counter back to the in itially loaded value. the cycle before the increment that result s in all unmasked counter bits to become 1s, a counter interrupt flag (cntint ) is asserted if the counter is incremented again. th is increment caus es the counter to reach its maximum value and the next increment returns the counter register to its initial value that was stored in the mirror register if wrp is deasserted. if wrp is asserted, the unmasked portion of the counter is filled with 0 instead. the example shown in figure 8 on page 17 shows an example of the cydd36s18v18 device with the mask register loaded with a mask value of 00007f unmasking the seven least significant bits. setting the mask register to this value enables the counter to access the entire memory space. the address counter is then loaded with an initial value of 000005 assuming wrp is deasserted. the masked bits, the seventh address through the twenty-first address, do not in crement in an increment operation. the counter address starts at address 000005 and increments its internal address value until it reaches the mask register value of 00007f. the counter wraps around the memory block to location 000005 at the next count. cntint is issued when the counter reaches the maximum ?1 count. hold operation the value of all three registers is constantly maintained unchanged for an unlimited number of clock cycles. this operation is useful in applicatio ns where wait states are needed or when address is available a few cycles ahead of data in a shared bus interface. retransmit retransmit enables repeated access to the same block of memory without the need to reload the initial address. an internal mirror register stores the addr ess counter value last loaded. while ret is asserted low, the counter continues to wrap back to the value in the mirror register independent of the state of wrp . counter interrupt the counter interrupt (cntint ) is asserted low one clock cycle before an increment operation t hat results in the unmasked portion of the counter register being all 1s. it is deasserted by counter reset, counter load, counter increment, mask reset, mask load, and mrst . counting by two when the two least significant bits of the mask register are 10, the counter increments by two. counting by four when the two least significant bits of the mask register are 00, the counter increments by four. mailbox interrupts use the upper two memory locations for message passing and permit communications between ports. table 8 on page 17 shows the interrupt operation for both ports. the highest memory location is the mailbox for the right port and the maximum address ? 1 is the mailbox for the left port. when one port writes to the other port?s mailbox, the int flag of the port that the mailbox belongs to is asserted low. the int flag remains asserted until the mailbox location is read by the other port. when a port reads its mailbox, the int flag is deasserted high after one cycle of latency with respect to the input clock of the port to which the mailbox belongs and is independent of oe . as shown in table 8 on page 17 , to set the int r flag, a write operation by the left port to address 1fffff asserts int r low. a valid read of the 1fffff location by the right port resets int r high after one cycle of latency with respect to the right port?s clock. you must activate at leas t one byte enable to set or reset the mailbox interrupt. note 31. the cyd36s18v18 device has 21 address bits. the cyd36s36v18 and cyd18s18v18 devices have 20 address bits. the cyd36s72v18, c yd18s36v18, and cyd09s18v18 devices have 19 address bits. the cyd18s72v18 and cyd09s36v18 devices have 18 address bits. the cyd09s72v18 device has 17 address bits. the cyd02s36v18 has 16 address bits. [+] feedback FULLFLEX document number: 38-06082 rev. *k page 16 of 52 figure 7. counter, mask, and mirror logic block diagram figure 7 shows the counter, mask, and mirror logic block diagram. [32] note 32. the cyd36s18v18 device has 21 address bits. the cyd36s36v18 and cyd18s18v18 devices have 20 address bits. the cyd36s72v18, c yd18s36v18, and cyd09s18v18 devices have 19 address bits. the cyd18s72v18 and cyd09s36v18 devices have 18 address bits. the cyd09s72v18 device has 17 address bits. the cyd02s36v18 has 16 address bits. from mask register mirror counter address decode ram array wrap 1 0 increment logic 1 0 +1 +2 1 0 wrap detect from mask from counter to coun- ter bit 0 and 1 wrap 20 20 20 20 20 1 0 load/increment cnt/msk cnten a cntrst c decode logic a mask register counter/ address register from address lines to readback and address decode 20 20 mrst ret +4 [+] feedback FULLFLEX document number: 38-06082 rev. *k page 17 of 52 figure 8. programmable counter-mask register operation with wrp deasserted figure 8 shows the programmable counter-mask operation with wrp deasserted. [36, 38] table 8. interrupt operation example ta b l e 8 shows the interrupt operation example. [33, 34, 35, 37, 38] function left port right port r/w l ce l a 0l?20l int l r/w r ce r a 0r?20r int r set right int r flag l l max address x x x x l reset right int r flag x x x x h l max address h set left int l flag x x x l l l max address?1 x reset left int l flag h l max address?1 h x x x x 2 20 2 19 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 20 2 19 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 20 2 19 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 20 2 19 2 6 2 1 2 5 2 2 2 4 2 3 2 0 h h l h 11 0s 1 0 1 0 1 11 00 xs 0 x 1 x 0 01 11 xs 1 x 1 x 1 11 00 xs 0 x 1 x 0 01 masked address unmasked address mask register lsb address counter lsb cntint example: load counter-mask register = 00007f load address counter = 000005 max address value max + 1 address value 0 2 7 x 2 7 x 2 7 x 2 7 notes 33. ce is internal signal. ce = low if ce 0 = low and ce 1 = high. for a single read operation, ce only needs to be asserted once at the rising edge of the c and is deasserted after that. data is out after the following c edge and is tri-stated after the next c edge. 34. oe is ?don?t care? for mailbox operation. 35. at least one of be0 , be1 , be2 , be3 , be4 , be5 , be6 , or be7 must be low. 36. the ?x? in this diagram represents the counter?s upper bits. 37. ?x? = don?t care, ?h? = high, ?l? = low. 38. the cyd36s18v18 device has 21 address bits. the cyd36s36v18 and cyd18s18v18 devices have 20 address bits. the cyd36s72v18, c yd18s36v18, and cyd09s18v18 devices have 19 address bits. the cyd18s72v18 and cyd09s36v18 devices have 18 address bits. the cyd09s72v18 device has 17 address bits. the cyd02s36v18 has 16 address bits. [+] feedback FULLFLEX document number: 38-06082 rev. *k page 18 of 52 master reset the FULLFLEX family of dual ports undergoes a complete reset when mrst is asserted. mrst must be driven by vddio l referenced levels. the mrst is asserted asynchronously to the clocks and must remain asserted for at least t rs . when asserted mrst deasserts ready , initializes the internal burst counters, internal mirror registers, and internal busy addresses to zero. it also initializes the internal mask register to all 1s. all mailbox interrupts (int ), busy address outputs (busy ), and burst counter interrupts (cntint ) are deasserted upon master reset. additionally, do not release mrst until all power supplies including vref are fully ram ped and all port clocks and mode select inputs (lowspd , zq, cqen, ftsel , and portstd) are valid and stable. this begins calibration of the dll and vim circuits. ready is asserted within 1024 clock cycles. ready is a wired or capable output with a strong pull up and weak pull down. up to four outputs may be connected together. for faster pull down of the signal, connec t a 250 ohm resistor to vss. if the dll and vim circuits are disabled for a port, the port is operational within five clo ck cycles. however, the ready is asserted within 160 clock cycles. ieee 1149.1 serial boundary scan (jtag) the FULLFLEX families incorporate an ieee 1149.1 serial boundary scan test access port (tap). the tap operates using jedec-standard 3.3 v or 2.5 v io logic levels depending on the vttl power supply. it is composed of four input connections and one output connection required by the test logic defined by the standard. table 9. jtag idcode register definitions part number configuration value cyd36s72v18 512 k 72 0c026069h (2) cyd36s36v18 1024 k 36 0c023069h cyd36s18v18 2048 k 18 0c024069h cyd18s72v18 256 k 72 0c025069h cyd18s36v18 512 k 36 0c026069h cyd18s18v18 1024 k 18 0c027069h cyd09s72v18 128 k 72 0c028069h cyd09s36v18 256 k 36 0c029069h cyd09s18v18 512 k 18 0c02a069h cyd02s36v18 64 k 36 0c030069h table 10. scan registers sizes register name bit size instruction 4 bypass 1 identification 32 boundary scan n [39] table 11. instruction identification codes instruction code description extest 0000 captures the input and output ring cont ents. places the bsr between the tdi and tdo. bypass 1111 places the byr between tdi and tdo. idcode 1011 loads the idr with the vendor id code and places the register between tdi and tdo. highz 0111 places byr between tdi and tdo. forces all FULLFLEX72 and FULLFLEX36 output drivers to a high z state. clamp 0100 controls boundary to 1 or 0. places byr between tdi and tdo. sample/preload 1000 captures the input and output ring contents. places bsr between tdi and tdo. reserved all other codes other combinations are reserved. do not use other than the mentioned combinations. note 39. details of the boundary scan length is found in the bsdl file for the device. [+] feedback FULLFLEX document number: 38-06082 rev. *k page 19 of 52 maximum ratings exceeding maximum ratings may impair the useful life of the device. user guidelines are not tested. storage temperature............................... ?65 c to + 150 c ambient temperature with power applied .......................................... ?55 c to + 125 c supply voltage to ground potential ..............?0.5 v to + 4.1 v dc voltage applied to outputs in high z state ...................... ?0.5 v to v ddio + 0.5 v dc input voltage ............................... ?0.5 v to v ddio + 0.5 v output current into outputs (low) ............................. 20 ma static discharge voltage........................................... > 2200 v (jedec jesd8-6, jesd8-b) latch-up current ..................................................... > 200 ma operating range range ambient temperature vcore commercial 0 c to +70 c 1.8 v ? 100 mv 1.5 v ?? 80 mv industrial ?40 c to +85 c 1.8 v ? 100 mv 1.5 v ?? 80 mv power supply requirements min typ max lvttl vddio 3.0 v 3.3 v 3.6 v 2.5 v lvcmos vddio 2.3 v 2.5 v 2.7 v hstl vddio 1.4 v 1.5 v 1.9 v 1.8 v lvcmos vddio 1.7 v 1.8 v 1.9 v 3.3 v vttl 3.0 v 3.3 v 3.6 v 2.5 v vttl 2.3 v 2.5 v 2.7 v hstl vref 0.68 v 0.75 v 0.95 v electrical characteristics over the operating range parameter description configuration all speed bins unit min typ max v oh output high voltage (v ddio = min, i oh = ?8 ma) lvttl 2.4 [40] ??v (v ddio = min, i oh = ?4 ma) hstl (dc) [41] vddio ? 0.4 [40] ??v (v ddio = min, i oh = ?4 ma) hstl (ac) [41] vddio ? 0.5 [40] ??v (v ddio = min, i oh = ?6 ma) 2.5 v lvcmos 1.7 [40] ??v (v ddio = min, i oh = ?4 ma) 1.8 v lvcmos vddio ? 0.45 [40] ??v v ol output high voltage (v ddio = min, i ol = 8 ma) lvttl ? ? 0.4 [40] v (v ddio = min, i ol = 4 ma) hstl(dc) [41] ??0.4 [40] v (v ddio = min, i ol = 4 ma) hstl (ac) [41] ??0.5 [40] v (v ddio = min, i ol = 6 ma) 2.5 v lvcmos ? ? 0.7 [40] v (v ddio = min, i ol = 4 ma) 1.8 v lvcmos ? ? 0.45 [40] v v ih input high voltage lvttl 2 ? vddio + 0.3 v hstl(dc) [41] vref + 0.1 ? vddio + 0.3 v 2.5 v lvcmos 1.7 ? v 1.8 v lvcmos 0.65 vddio ? v v il input low voltage lvttl ?0.3 ? 0.8 v hstl(dc) [41] ?0.3 ? vref ? 0.1 v 2.5 v lvcmos ? ? 0.7 v 1.8 v lvcmos ? ? 0.35 vddio v notes 40. these parameters are met with vim disabled. 41. the dc specifications are measured under steady state conditions. the ac specificat ions are measured while switching at spee d. ac vih/vil in hstl mode are measured with 1 v/ns input edge rates. [+] feedback FULLFLEX document number: 38-06082 rev. *k page 20 of 52 ready v oh output high voltage (v ddio = min, i oh = ?24 ma) lvttl 2.7 [42] ??v (v ddio = min, i oh = ?12 ma) hstl(dc) [43] vddio ? 0.4 [42] ??v (v ddio = min, i oh = ?12 ma) hstl (ac) [43] vddio ? 0.5 [42] ??v (v ddio = min, i oh = ?15 ma) 2.5 v lvcmos 2.0 [42] ??v (v ddio = min, i oh = ?12 ma) 1.8 v lvcmos vddio ? 0.45 [42] ??v ready v ol output high voltage (v ddio = min, i o = 0.12 ma) lvttl ? ? 0.4 [42] v (v ddio = min, i ol = 0.12 ma) hstl(dc) [43] ??0.4 [42] v (v ddio = min, i ol = 0.12 ma) hstl (ac) [43] ??0.5 [42] v (v ddio = min, i ol = 0.15 ma) 2.5 v lvcmos ? ? 0.7 [42] v (v ddio = min, i ol = 0.08 ma) 1.8 v lvcmos ? ? 0.45 [42] v i oz output leakage current ?10 ? 10 ? a i ix1 input leakage current except tdi, tms, mrst , portstd ?10 ? 10 ? a i ix2 input leakage current tdi, tms, mrst ?300 ? 10 ? a i ix3 input leakage current portstd ?10 ? 300 ? a electrical characteristics (continued) over the operating range parameter description configuration all speed bins unit min typ max notes 42. these parameters are met with vim disabled. 43. the dc specifications are measured under steady state conditions. the ac specificat ions are measured while switching at spee d. ac vih/vil in hstl mode are measured with 1 v/ns input edge rates. [+] feedback FULLFLEX document number: 38-06082 rev. *k page 21 of 52 electrical characteristics over the operating range parameter description configuration -200 -167 unit typ max typ max i cc operating current (v core = max, i out = 0 ma) outputs disabled 512 k 72 commercial 1440 1800 1280 1620 ma industrial ? ? 1330 1730 ma 1024 k 36 commercial 1180 1500 1050 1350 ma industrial ? ? 1110 1470 ma 2048 k 18 commercial 1130 1430 1000 1290 ma industrial ? ? 1060 1410 ma 256 k 72 commercial 800 980 700 880 ma industrial 820 1030 730 930 ma 512 k 36 commercial 640 800 570 720 ma industrial 670 860 590 780 ma 1024 k 18 commercial 610 770 540 690 ma industrial 640 830 570 750 ma 128 k 72 commercial 640 790 560 700 ma industrial 660 830 580 740 ma 256 k 36 commercial 540 640 470 570 ma industrial 550 670 490 600 ma 512 k 18 commercial 550 660 480 580 ma industrial 570 690 500 610 ma 64 k 36 commercial ? ? ? ? ma industrial ? ? ? ? ma [+] feedback FULLFLEX document number: 38-06082 rev. *k page 22 of 52 i sb1 standby current (both ports ttl level) ce l and ce r ? v ih , f = f max 512 k 72 commercial 1000 1250 920 1160 ma industrial ? ? 970 1260 ma 1024 k 36 commercial 910 1140 820 1050 ma industrial ? ? 880 1160 ma 2048 k 18 commercial 890 1110 810 1030 ma industrial ? ? 860 1140 ma 256 k 72 commercial 500 630 460 580 ma industrial 530 680 490 630 ma 512 k 36 commercial 460 570 410 530 ma industrial 480 630 440 580 ma 1024 k 18 commercial 450 560 410 520 ma industrial 470 610 430 570 ma 128 k 72 commercial 400 490 360 450 ma industrial 420 540 380 490 ma 256 k 36 commercial 380 440 340 400 ma industrial 390 470 360 430 ma 512 k 18 commercial 390 460 350 410 ma industrial 410 480 370 440 ma 64 k 36 commercial ? ? ? ? ma industrial ? ? ? ? ma electrical characteristics (continued) over the operating range parameter description configuration -200 -167 unit typ max typ max [+] feedback FULLFLEX document number: 38-06082 rev. *k page 23 of 52 i sb2 standby current (one port ttl or cmos level) ce l | ce r ? v ih , f = f max 512 k 72 commercial 1300 1570 1160 1410 ma industrial ? ? 1210 1520 ma 1024 k 36 commercial 1090 1330 980 1210 ma industrial ? ? 1030 1330 ma 2048 k 18 commercial 1040 1270 930 1160 ma industrial ? ? 980 1270 ma 256 k 72 commercial 650 790 580 710 ma industrial 680 840 610 760 ma 512 k 36 commercial 550 670 490 610 ma industrial 570 730 520 670 ma 1024 k 18 commercial 520 640 470 580 ma industrial 550 690 490 640 ma 128 k 72 commercial 520 630 460 560 ma industrial 550 670 480 610 ma 256 k 36 commercial 460 530 400 470 ma industrial 480 560 430 500 ma 512 k 18 commercial 460 530 410 480 ma industrial 480 560 430 510 ma 64 k 36 commercial ? ? ? ? ma industrial ? ? ? ? ma electrical characteristics (continued) over the operating range parameter description configuration -200 -167 unit typ max typ max [+] feedback FULLFLEX document number: 38-06082 rev. *k page 24 of 52 electrical characteristics over the operating range parameter description configuration all speed bins unit typ max i sb3 standby current (both ports cmos level) ce l and ce r ? v core ? 0.2 v, f = 0 512 k 72 commercial 410 590 ma industrial 460 700 ma 1024 k 36 commercial 410 590 ma industrial 460 700 ma 2048 k 18 commercial 410 590 ma industrial 460 700 ma 256 k 72 commercial 210 300 ma industrial 230 350 ma 512 k 36 commercial 210 300 ma industrial 230 350 ma 1024 k 18 commercial 210 300 ma industrial 230 350 ma 128 k 72 commercial 150 200 ma industrial 170 220 ma 256 k 36 commercial 150 200 ma industrial 170 220 ma 512 k 18 commercial 150 200 ma industrial 170 220 ma table 12. capacitance signals packages cyd18s72v18 cyd09s72v18 cyd18s36v18 cyd09s36v18 cyd02s36v18 cyd18s18v18 cyd09s18v18 cyd36s72v18 cyd36s36v18 cyd36s18v18 oe 12 pf 12 pf 20 pf 20 pf be , dq 10 pf 18 pf 16 pf 30 pf all other signals 10 pf 10 pf 16 pf 16 pf [+] feedback FULLFLEX document number: 38-06082 rev. *k page 25 of 52 ac test load and waveforms figure 9. output test load for lvttl/cmos figure 10. output test load for hstl figure 11. hstl input waveform output 50 ohm 50 ohm vth = 1.5 v for lvtt l vth = 50% vddio for 2.5 v cmo s vth = 50% vddio for 1.8 v cmo s zq rq=250 ohm device under test v ref v ref = nc test point c = 10pf ready r=250 ohm vth output 50 ohm 50 ohm vth = 50% vddio zq rq=250 ohm device under test v ref v ref = 0.75v test point c= 10pf for sdr r=250 ohm ready vth [+] feedback FULLFLEX document number: 38-06082 rev. *k page 26 of 52 switching characteristics over the operating range table 13. sdr mode, signals affected by dll parameter description dll on (lowspd =1) [46] dll off (lowspd =0) [46] -200 -167 unit min max min max min max t cd2 [49] c rise to dq valid for pipelined mode ?3.30 [45, 48] ?4.00 [45, 48] ?6.00 [45, 48] ns t ccq [49] c rise to cq rise 1.00 3.30 [48] 1.00 4.00 [48] 1.00 6.00 [48] ns t ckhz2 [44, 49] c rise to dq output high z in pipelined mode 1.00 3.30 [45, 48] 1.00 4.00 [45, 48] 1.00 6.00 [45, 48] ns t cklz2 [44, 49] c rise to dq output low z in pipelined mode 1.00 ? 1.00 ? 1.00 ? ns table 14. sdr mode parameter description -200 -167 unit min max min max f max (p ipelined ) maximum operating frequency for pipelined mode 100 200 100 167 mhz f max (f low through ) maximum operating frequency for flow through mode ? 77 ? 66.7 mhz t cyc (p ipelined ) c clock cycle time for pipelined mode 5.00 [48] 10.00 6.00 [48] 10.00 ns t cyc (f low x through ) c clock cycle time for flow through mode 13.00 [48] ?15.00 [48] ?ns t ckd c clock duty time 45 55 45 55 % t sd data input setup time to c rise hstl 1.8 v lvcmos 1.50 [45, 48] ?1.70 [45, 48] ?ns 2.5 v lvcmos 3.3 v lvttl 1.75 [45, 48] ?1.95 [45, 48] ns t hd [47] data input hold time after c rise 0.5 ? 0.5 ? ns t sac address and control input setup time to c rise hstl 1.8 v l vcmos 1.50 [45, 47, 48] ?1.70 [45, 47, 48] ?ns 2.5 v lvcmos 3.3 v lvttl 1.75 [45, 47, 48] ?1.95 [45, 47, 48] ?ns t hac [47] address and control input hold time after c rise 0.50 ? 0.60 ? ns t oe output enable to data valid ? 4.40 [45, 48] ?5.00 [45, 48] ns t olz [44] oe to low z 1.00 ? 1.00 ? ns notes 44. parameters specified with the load capacitance in figure 9 on page 25 and figure 10 on page 25 . 45. for the x18 devices, add 200 ps to this parameter in table 14 . 46. test conditions assume a signal transition time of 2 v/ns. 47. add 300 ps to this timing for 36m devices. 48. add 15% to this parameter if a vcore of 1.5 v is used. 49. this parameter assumes input clock cycle to cycle jitter of 0ps. [+] feedback FULLFLEX document number: 38-06082 rev. *k page 27 of 52 t ohz [50] oe to high z 1.00 4.40 [51, 52] 1.00 5.00 [51, 52] ns t cd1 c rise to dq valid for flow through mode (lowspd = 0) ?9.00 [51, 52] ? 11.00 [51, 52] ns t ca1 c rise to address readback valid for flow through mode ? 9.00 [52] ? 11.00 [52] ns t ca2 c rise to address readback valid for pipelined mode ? 5.00 [52] ?6.00 [52] ns t dc [53] dq output hold after c rise 1.00 ? 1.00 ? ns t jit clock input cycle to cycle jitter ? +/- 200 ? +/- 200 ps t cqhqv [53] echo clock (cq) high to output valid hstl 1.8 v lvcmos ?0.70 [51] ?0.80 [51] ns 2.5 v lvcmos 3.3 v lvttl ?0.80 [51] ?0.90 [51] ns t cqhqx [53] echo clock (cq) high to output hold hstl 1.8 v lvcmos ?0.70 ? ?0.80 ? ns 2.5 v lvcmos 3.3 v lvttl ?0.85 ? ?0.95 ? ns t ckhz1 [50] c rise to dq output high z in flow through mode 1.00 9.00 [51, 52] 1.00 11.00 [51, 52] ns t cklz1 [50] c rise to dq output low z in flow through mode 1.00 ? 1.00 ? ns t ac address output hold after c rise 1.00 ? 1.00 ? ns t ckhza1 [50] c rise to address output high z for flow through mode 1.00 9.00 [52] 1.00 11.00 [52] ns t ckhza2 [50] c rise to address output high z for pipelined mode 1.00 5.00 [52] 1.00 6.00 [52] ns t cklza [50] c rise to address output low z 1.00 ? 1.00 ? ns t scint c rise to cntint low 1.00 3.30 [52] 1.00 4.00 [52] ns t rcint c rise to cntint high 1.00 3.30 [52] 1.00 4.00 [52] ns t sint c rise to int low 0.50 7.00 [52] 0.50 8.00 [52] ns t rint c rise to int high 0.50 7.00 [52] 0.50 8.00 [52] ns t bsy c rise to busy valid 1.00 3.30 [52] 1.00 4.00 [52] ns table 14. sdr mode (continued) parameter description -200 -167 unit min max min max notes 50. parameters specified with the load capacitance in figure 9 on page 25 and figure 10 on page 25 . 51. for the x18 devices, add 200 ps to this parameter in table 14 . 52. add 15% to this parameter if a vcore of 1.5 v is used. 53. this parameter assumes input clock cycle to cycle jitter of 0ps. [+] feedback FULLFLEX document number: 38-06082 rev. *k page 28 of 52 table 15. master reset timing parameter description -200 -167 unit min max min max t pup power-up time 1 ? 1 ? ms t rs master reset pulse width 5 ? 5 ? cycles t rsr master reset recovery time 5 ? 5 ? cycles t rsf master reset to outputs inactive/hi z ? 15 ? 18 ns t rdy [54] master reset release to port ready ? 1024 ? 1024 cycles t cordy [55] c rise to port ready ? 9.5 [56] ?11 [56] ns table 16. jtag timing parameter description -200 -167 unit min max min max f jtag jtag tap controller frequency ? 20 ? 20 mhz t tcyc tck cycle time 50?50?ns t th tck high time 20 ? 20 ? ns t tl tck low time 20?20?ns t tmss tms setup to tck rise 10 ? 10 ? ns t tmsh tms hold to tck rise 10?10?ns t tdis tdi setup to tck rise 10 ? 10 ? ns t tdih tdi hold to tck rise 10 ? 10 ? ns t tdov tck low to tdo valid ? 10 ? 10 ns t tdox tck low to tdo invalid 0 ? 0 ? ns t jxz tck low to tdo high z ? 15 ? 15 ns t jzx tck low to tdo active ?15?15ns t jzx tck low to tdo active ?15?15ns . notes 54. ready is a wired or capable output with a weak pull-down. for a decreased falling delay, connect a 250- ? resistor to vss. 55. add this propagation delay after t rdy for all master reset operations. 56. add 15% to this parameter if a vcore of 1.5 v is used. [+] feedback FULLFLEX document number: 38-06082 rev. *k page 29 of 52 switching waveforms figure 12. jtag timing figure 13. master reset [57] test clock test mode select tck tms test data-in tdi te s t d a t a - o u t tdo t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdox t tdov t pup t rs t rsf t rsr v core mrst c ready all address & data all other inputs t rdy t cordy ~ ~ ~ ~ ~ ~ note 57. ready is a wired or capable output with a weak pull-do wn. for a decreased falling delay, connect a 250- ? resistor to vss. [+] feedback FULLFLEX document number: 38-06082 rev. *k page 30 of 52 figure 14. read cycle for pipelined mode figure 15. write cycle for pipelined and flow through modes switching waveforms (continued) c t cyc r/ w a 2 pipelined stages a n a n+1 a n+2 a n+3 a n+4 a n+5 a n+6 dq x-1 dq x dq n dq n+1 dq n+2 dq n+3 dq n+4 t dc t cd2 t sac t hac dq ce oe t cyc c r/w a a n a n+1 a n+2 a n+3 a n+4 a n+5 a n+6 dq n dq n+1 dq n+2 dq n+3 dq n+4 dq n+5 dq n+6 2 pipelined stages t sd t hd dq ce [+] feedback FULLFLEX document number: 38-06082 rev. *k page 31 of 52 figure 16. read with address counter advance for pipelined mode figure 17. read with address coun ter advance for flow through mode switching waveforms (continued) c t cyc dq x-1 dq x dq n dq n+1 dq n+2 a internal ads address cnten a n+1 a n a n+2 a n+3 dq n+3 dq a n t cyc c t sac t hac t hac t dc t cd1 t sac read external address read w ith counter counter hold read with counter dqx dqn + 1 dqn + 2 dqn + 3 dqn + 4 dqn an a dq cnten ads [+] feedback FULLFLEX document number: 38-06082 rev. *k page 32 of 52 figure 18. port-to-port wr ite?read for pipelined mode figure 19. chip enable read for pipelined mode switching waveforms (continued) c l a n dq n left port r/w l c r right port a n r/w r dq n t cd2 t dc t sac t hac t cyc t cyc t ccs a l dq l a r dq r c r/w a a n a n+1 a n+2 a n+3 a n+4 a n+5 a n+6 t sac t hac t cyc ce0 ce1 dq dq n dq n+3 t cd2 t dc t cklz2 [+] feedback FULLFLEX document number: 38-06082 rev. *k page 33 of 52 figure 20. oe controlled write for pipelined mode figure 21. oe controlled write for flow through mode switching waveforms (continued) c r/w a a x+1 a x+2 a x+3 a n a n+1 a n+2 a n+3 t cyc dq x-1 dq x dq x+1 dq n dq n+1 dq n+2 dq n+3 oe dq t ohz c r/w a a x+1 a x+2 a x+3 a n a n+1 a n+2 a n+3 t cyc dq x dq x+1 dq x+2 dq n dq n+1 dq n+2 dq n+3 oe dq t ohz [+] feedback FULLFLEX document number: 38-06082 rev. *k page 34 of 52 figure 22. byte-enable read for pipelined mode switching waveforms (continued) c r/w a a n a n+1 a n+2 a n+3 t cyc be7 be6 be5 be4 be3 be2 be1 be0 dq 63:71 dq 54:62 dq 45:53 dq 36:44 dq 27:35 dq 18:26 dq 9:17 dq 0:8 dq n+1(63:71) dq n+1(54:62) dq n+1(27:35) dq n+2(45:53) dq n+2(36:44) dq n+2(18:26) dq n+3(9:17) dq n+3(0:8) t cklz2 t ckhz2 [+] feedback FULLFLEX document number: 38-06082 rev. *k page 35 of 52 figure 23. port-to-port write -to-read for flow through mode switching waveforms (continued) t hd t sd t cd1 t dc t dc t sac t hac t cd1 t ccs t hac t sac match valid no match no match match valid valid c l r/w l c r a l dq l r/w r a r dq r [+] feedback FULLFLEX document number: 38-06082 rev. *k page 36 of 52 figure 24. busy address readback for pipelined and flow through modes, cnt/msk = ret = low [58] figure 25. read cycle for flow through mode switching waveforms (continued) internal a match+2 a match+3 a match+4 t cyc c busy ~ ~ ~ ~ ~ ~ cnten ads external a match t ca2 t ac address pipelined ~ a match t ca1 t ac flow through address external address t cyc t sac t hac t ckhz1 t dc t oe t olz t ohz t dc t cd1 t cklz1 an t hac t sac ce 1 ce 0 c an + 1 an + 3 an + 2 dqn dqn + 1 dqn + 2 r/w oe ben a dq note 58. a match is the matching address that is reported on the address bus of the losing port. the counter operation selected for reporting t he address is ?busy address readback.? [+] feedback FULLFLEX document number: 38-06082 rev. *k page 37 of 52 figure 26. read-to-write for pipelined mode (oe = v il ) [59, 60, 61] figure 27. read-to-write for pipelined mode (oe controlled) [62, 63] switching waveforms (continued) c a a x a n a n+1 a n+2 t cyc dq x-2 dq x-1 dq x dq n dq n+1 dq n+2 t ch t cl t sac t hac t sac t hac t dc t cd2 t ckhz2 t sd t hd r/w dq t cklz2 c r/w a a x a x+1 a x+2 a n a n+1 a n+2 a n+3 t cyc dq x-2 dq x-1 dq x dq n dq n+1 dq n+2 dq n+3 t sac t hac t ohz t sd t hd oe dq notes 59. when oe = v il , the last read operation is enabled to complete before the dq bus is tri-stated and the user is enabled to drive write data. 60. two dummy writes are issued to accomplish bus tur naround. the third instruction is the first valid write. 61. chip enable or all byte enables are held inactive during the two dummy writes to avoid data corruption. 62. oe is deasserted and t ohz enabled to elapse before the first write operation is issued. 63. any write scheduled to complete after oe is deasserted is pre-empted. [+] feedback FULLFLEX document number: 38-06082 rev. *k page 38 of 52 figure 28. read-to-write-to-r ead for flow th rough mode (oe = low) switching waveforms (continued) t hd t sd t sac t ckhz1 t dc t cd1 t cd1 t sac t cyc t hac t dc t cd1 t cd1 t cklz1 read read write nop an an + 1 an + 2 an + 2 an + 3 an + 4 dqn + 2 dqn dqn + 1 dqn + 3 c r/w ben ce 1 dq out dq in a t hac ce 0 [+] feedback FULLFLEX document number: 38-06082 rev. *k page 39 of 52 figure 29. read-to-w rite-to-read for flow through mode (oe controlled) switching waveforms (continued) t cd1 t cklz1 t hd t sd t ohz t dc t cd1 t hac t sac t cyc t dc t cd1 t oe read read write an an + 1 an + 2 an + 3 an + 4 an + 5 dqn + 2 dqn + 3 dqn dqn + 4 c r/w ben ce 1 dq out dq in a oe t hac t sac ce 0 [+] feedback FULLFLEX document number: 38-06082 rev. *k page 40 of 52 figure 30. busy timing, write-write collision for pipelined and flow through modes, clock timing violates t ccs . (flag both ports) switching waveforms (continued) port a a r/w t bsy t bsy busy port b < t ccs a r/w t bsy t bsy busy c losing port c a r/w t bsy t bsy busy winning port a r/w c t ccs match c figure 31. busy timing, write-write collision for pipelined and flow through modes, clock timing meets t ccs . (flag losing port) busy [+] feedback FULLFLEX document number: 38-06082 rev. *k page 41 of 52 figure 32. read with echo cloc k for pipelined mode (cqen = high) switching waveforms (continued) c r/ w a a n a n+1 a n+2 a n+3 a n+4 a n+5 a n+6 dq x-1 dq x dq n dq n+1 dq n+2 dq n+3 dq n+4 t sac t hac dq cq1 cq1 cq0 cq0 t ccq t cqhqv t cqhqx [+] feedback FULLFLEX document number: 38-06082 rev. *k page 42 of 52 figure 33. mailbox interrupt output switching waveforms (continued) t cyc c l a l r/ w l dq l int r c r a r r/ w r dq r a max dq max a max t sint t rint [+] feedback FULLFLEX document number: 38-06082 rev. *k page 43 of 52 ordering information 512 k 72 (36-mbit) 1.8 v/1.5 v synchronous cyd36s72v18 dual port sram speed (mhz) ordering code package diagram package type operating range 200 cyd36s72v18-200bgxc 001-07825 484-ball ball grid array 27 mm 27 mm with 1.0 mm pitch (pb-free) commercial 167 cyd36s72v18-167bgxi 001-07825 484-ball ball grid array 27 mm 27 mm with 1.0 mm pitch (pb-free) industrial 256 k 72 (18-mbit) 1.8 v/1.5 v synchr onous cyd18s72v18 dual port sram speed (mhz) ordering code package diagram package type operating range 200 cyd18s72v18-200bgxi 51-85218 484-ball ball grid array 23 mm 23 mm with 1.0 mm pitch (pb-free) industrial 200 cyd18s72v18-200bgi 51-85218 484-ball ball grid array 23 mm 23 mm with 1.0 mm pitch industrial 167 cyd18s72v18-167bgxc 51-85218 484-ball ball grid array 23 mm 23 mm with 1.0 mm pitch (pb-free) commercial 167 cyd18s72v18-167bgc 51-85218 484-ball ball grid array 23 mm 23 mm with 1.0 mm pitch commercial 167 cyd18s72v18-167bgi 51-85218 484-ball ball grid array 23 mm 23 mm with 1.0 mm pitch industrial 128 k 72 (9-mbit) 1.8 v/1.5 v synchronous cyd09s72v18 dual port sram speed (mhz) ordering code package diagram package type operating range 200 cyd09s72v18-200bgxi 51-85218 484-ball ball grid array 23 mm 23 mm with 1.0 mm pitch (pb-free) industrial 167 cyd09s72v18-167bbxc 51-85218 484-ball ball grid array 23 mm 23 mm with 1.0 mm pitch (pb-free) commercial 1024 k 36 (36-mbit) 1.8 v/1.5 v synchronous cyd36s36v18 dual port sram speed (mhz) ordering code package diagram package type operating range 200 cyd36s36v18-200bgxc 001-07825 484-ball ball grid array 27 mm 27 mm with 1.0 mm pitch (pb-free) commercial 167 cyd36s36v18-167bgxc 001-07825 484-ball ball grid array 27 mm 27 mm with 1.0 mm pitch (pb-free) commercial 167 cyd36s36v18-167bgxi 001-07825 484-ball ball grid array 27 mm 27 mm with 1.0 mm pitch (pb-free) industrial 512 k 36 (18-mbit) 1.8 v/1.5 v synchr onous cyd18s36v18 dual port sram speed (mhz) ordering code package diagram package type operating range 200 cyd18s36v18-200bbaxi 51-85108 256-ball ball grid array 17 mm 17 mm with 1.0 mm pitch (pb-free) industrial 167 cyd18s36v18-167bbai 51-85108 256-ball ball grid array 17 mm 17 mm with 1.0 mm pitch industrial [+] feedback FULLFLEX document number: 38-06082 rev. *k page 44 of 52 256 k 36 (9-mbit) 1.8 v/1.5 v synchronous cyd09s36v18 dual port sram speed (mhz) ordering code package diagram package type operating range 200 cyd09s36v18-200bbxc 51-85108 256-ball ball grid array 17 mm 17 mm with 1.0 mm pitch (pb-free) commercial 200 cyd09s36v18-200bbxi 51-85108 256-ball ball grid array 17 mm 17 mm with 1.0 mm pitch (pb-free) industrial 167 cyd09s36v18-167bbxc 51-85108 256-ball ball grid array 17 mm 17 mm with 1.0 mm pitch (pb-free) commercial 64 k 36 (2-mbit) 1.8 v or 1.5 v synchronous cyd02s36v18 dual port sram speed (mhz) ordering code package diagram package type operating range 200 cyd02s36v18-200bbc 51-85108 256-ball ball grid array 17 mm 17 mm with 1.0 mm pitch commercial ordering information (continued) [+] feedback FULLFLEX document number: 38-06082 rev. *k page 45 of 52 2048 k 18 (36-mbit) 1.8 v/1.5 v synchronous cyd36s18v18 dual port sram speed (mhz) ordering code package diagram package type operating range 200 cyd36s18v18-200bgxc 001-07825 484-ball ball grid array 27 mm 27 mm with 1.0 mm pitch (pb-free) commercial 167 cyd36s18v18-167bgxc 001-07825 484-ball ball grid array 27 mm 27 mm with 1.0 mm pitch (pb-free) commercial 167 cyd36s18v18-167bgxi 001-07825 484-ball ball grid array 27 mm 27 mm with 1.0 mm pitch (pb-free) industrial 1024 k 18 (18-mbit) 1.8 v/1.5 v synchronous cyd18s18v18 dual port sram speed mhz) ordering code package diagram package type operating range 200 cyd18s18v18-200bbaxi 51-85108 256-ball ball grid array 17 mm 17 mm with 1.0 mm pitch (pb-free) industrial 200 cyd18s18v18-200bbaxc 51-85108 256-ball ball grid array 17 mm 17 mm with 1.0 mm pitch (pb-free) commercial 167 cyd18s18v18-167bbaxi 51-85108 256-ball ball grid array 17 mm 17 mm with 1.0 mm pitch (pb-free) industrial 512 k 18 (9-mbit) 1.8 v/1.5 v synchronous cyd09s18v18 dual port sram speed (mhz) ordering code package diagram package type operating range 200 cyd09s18v18-200bbxc 51-85108 256-ball ball grid array 17 mm 17 mm with 1.0 mm pitch (pb-free) commercial 200 cyd09s18v18-200bbxi 51-85108 256-ball ball grid array 17 mm 17 mm with 1.0 mm pitch (pb-free) industrial 167 cyd09s18v18-167bbxi 51-85108 256-ball ball grid array 17 mm 17 mm with 1.0 mm pitch (pb-free) industrial ordering code definitions ordering information (continued) temperature range: x = c or i c = commercial; i = industrial package type: (xxxx = bg or bb or bba or bgx or bbx or bbax) bg, bb, bba = ball grid array bgx, bbx, bbax = ball grid array (pb-free) speed grade: xxx = 167 mhz / 200 mhz v18 = 1.8 v sxx = data width dxx = density in mb cy = cypress cy dxx v18 - xxx xxxx x sxx [+] feedback FULLFLEX document number: 38-06082 rev. *k page 46 of 52 package diagrams figure 34. 256-ball fp bga (17 17 mm), 51-85108 51-85108 *h [+] feedback FULLFLEX document number: 38-06082 rev. *k page 47 of 52 figure 35. 484-ball pbga (23 mm 23 mm 2.03 mm), 51-85218 package diagrams 51-85218 *a [+] feedback FULLFLEX document number: 38-06082 rev. *k page 48 of 52 acronyms document conventions units of measure figure 36. 484-ball pbga (27 mm 27 mm 2.33 mm), 001-07825 package diagrams 001-07825 *a acronym description bga ball grid array cmos complementary metal oxide semiconductor dll delay lock loop fpbga fine pitch ball gird array hstl high speed transceiver logic i/o input/output sdr single data rate sram static random access memory tck test clock tdi test data in tdo test data out tms test mode select vim variable impedance matching symbol unit of measure c degree celcius mhz mega hertz a micro amperes ma milli amperes ms milli seconds mv milli volts ns nano seconds pf pico farad vvolts wwatts [+] feedback FULLFLEX document number: 38-06082 rev. *k page 49 of 52 document history page document title: FULLFLEX? synchronous sdr dual port sram document number: 38-06082 rev. ecn no. submission date orig. of change description of change ** 302411 see ecn ydt new data sheet *a 334036 see ecn ydt corrected typo on page 1 reproduced pdf file to fix formatting errors *b 395800 see ecn spn added stat ement about no echo clo cks for flow through mode updated electrical characteristics added note 16 and 17 (1.5 v timing) added note 33 (timing for x18 devices) updated input edge rate (note 34) updated table 5 on deterministic access control logic added description of busy readback in deterministic access control section changed dummy write descriptions updated zq pins connection details updated note 24, b0 to be0 added power supply requirements to mrst and vc_sel added note 4 (vim disable) updated supply voltage to ground potential to 4.1 v updated parameters on table 15 updated and added parameters to table 16 updated x72 pinout to sdr only pinout updated 484 pbga pin diagram updated the pin definition of mrst updated the pin definition of vc_sel updated ready description to include wired or note updated master reset to include wired or note for ready updated minimum v oh value for the 1.8 v lvcmos configuration updated electrical characteristics to include i oh and i ol values updated electrical characteristics to include ready added i ix3 updated maximum input capacitance added notes 33 and 34removed notes 15 and 17 updated pin definitions for cq0, cq0 , cq1 , and cq1 removed -100 speed bin from table.1 selection guide changed voltage name from v ddq to v ddio changed voltage name from v dd to v core moved the mailbox interrupt timing diagram to be the final timing diagram updated the package type for the cyd36s18v18 parts updated the package type for the cyd36s18v18 parts updated the package type for the cyd18s18v18 parts updated the package type for the cyd18s36v18 parts included the package diagram for the 256-ball fbga (19 x 19 mm) bw256 included an oe controlled write for flow through mode switching waveform included a read with echo clock switching waveform updated figure 5 and figure 6 updated electrical characteristics for ready v oh and ready v updated electrical characteristics for v oh and v ol for the -167 and -133 speeds included a unit column for table 5 removed switching characteristic t ca from chart included t ohz in switching waveform oe controlled write for pipelined mode included t cklz2 in waveform read-to-write-to-read for flow through mode [+] feedback FULLFLEX document number: 38-06082 rev. *k page 50 of 52 *c 402238 see ecn kgh updated ac test load and waveforms included FULLFLEX36 sdr 484-ball bga pinout (top view) included FULLFLEX18 sdr 484-ball bga pinout (top view) included timing parameter t cordy *d 458131 see ecn ydt changed or dering information with pb -free part numbers removed vc_sel added io and core voltage adders removed references to bin drop for lv ttl/2.5 v lvcmos and 1.5 v core modes updated cin and cout updated icc, isb1, isb2 and isb3 tables updated busy address read back timing diagram added htsl input waveform removed hstl (ac) from dc tables added 484-ball 27 mmx27 mmx2.33 mm pbga package *e 470031 see ecn ydt changed vol of 1.8 v lvcmos to 0.45 v updated trsf vref is dnu when hstl is not used formatted pin description table changed vddio pins for 36m x 36 and 36m x 18 pinouts changed 36mx72 jtag idcode *f 500001 see ecn ydt dll chang e, added clock input cycle to cycle jitter modified dll description changed input capacitance table changed tccs number added note 31 *g 627539 see ecn qsl change all nc to dnu corrected switching waveform for (cqen = high) from both pipeline and flow through mode to only pipeline mode modified master reset description modified switching characteristics tables , extracted signals effected by the dll into one table and combine all other signals into one table updated package name added footnote for t hd, thac and tsac changed note 26 description document history page (continued) document title: FULLFLEX? synchronous sdr dual port sram document number: 38-06082 rev. ecn no. submission date orig. of change description of change [+] feedback FULLFLEX document number: 38-06082 rev. *k page 51 of 52 *h 2505003 see ecn vkn/ aesa modified footnote #1 removed 250 mhz speed bin added 2-mbit part and it?s related information changed ball name zq1 to dnu for 18m and lesser density devices added 256-ball (17 x 17 mm) bga package for 18m made portstd[1:0] left and right pins driven only by lvttl reference level for 1.8v lvcmos level, changed v ih(min) from 1.26v to 0.65 times v ddio and changed v il(max) from 0.36v to 0.35 times v ddio changed thd, thac specs for 36m from 0.6 ns/0.7 ns to 0.8 ns (see footnote# 32) updated ordering information table *i 2898491 07/01/2010 rame modified ?counter load operation? section on page 12 and in table7. on page 13. corrected typo in table 14. by making lowspd = 0 for t cd1 spec in the description. modified figure 16. on page 30. removed inactive parts from ordering information. updated packaging information. corrected ? counter interrupt operation? section in page 14 of the datasheet updated ordering information with the parts, cyd02s36v18-200bbc and cyd36s72v18-167bgi. *j 2995098 07/28/2010 rame updated ordering information and added ordering code definitions . added acronyms and units of measure . minor edits. *k 3267210 05/26/2011 admu updated electrical characteristics on page 21 (removed 133 mhz speed bin). updated switching characteristics on page 26 (removed 133 mhz speed bin). removed information for 4mb devices. updated ordering information . document history page (continued) document title: FULLFLEX? synchronous sdr dual port sram document number: 38-06082 rev. ecn no. submission date orig. of change description of change [+] feedback document number: 38-06082 rev. *k revised may 31, 2011 page 52 of 52 all products and company names mentioned in this document may be the trademarks of their respective holders. FULLFLEX ? cypress semiconductor corporation, 2005-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback |
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